Research
| Line 43: | Line 43: | ||
|- valign=top | |- valign=top | ||
| '''presented at''': | | '''presented at''': | ||
| − | | [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], | + | | width="450"| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016 |
|} | |} | ||
| Line 68: | Line 68: | ||
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
| − | | Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, | + | | width="450"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori |
|- valign=top | |- valign=top | ||
| '''presented at''': | | '''presented at''': | ||
| − | | [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], | + | | width="450"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016. |
|} | |} | ||
| Line 254: | Line 254: | ||
|- valign=top | |- valign=top | ||
| '''presented at''': | | '''presented at''': | ||
| − | | [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], | + | | width="450"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016. |
|} | |} | ||
Revision as of 09:30, 13 April 2017
We aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Our objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.
Logic Synthesis | |||||||||||||||||||||||||||||||||
|
We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes. 
| |||||||||||||||||||||||||||||||||
Fault Tolerance | |||||||||||||||||||||||
|
We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions 
| |||||||||||||||||||||||
Performance Modeling and Analysis | |||||||||||||
|
We introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. In order to find capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. 
| |||||||||||||
