Publications and Presentations

From NANOxCOMP H2020 Project
(Difference between revisions)
Jump to: navigation, search
(Logic Synthesis (WP1))
(Performance Modeling and Optimization (WP2))
Line 86: Line 86:
 
|}
 
|}
  
== Performance Modeling and Optimization (WP2) ==
+
== Performance Modeling and Optimization ==
  
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:2px solid #abd5f5; background:#f1f5fc;"

Revision as of 17:51, 11 April 2017

All materials are subject to copyrights.

Contents

Comprehensive

title: Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance
authors: Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori
presented at: Design, Automation, and Test in Europe (DATE), Lausanne, Switzerland, 2017.

PDF.png
Paper

PPT.jpg
Slides

title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani,
and Mehdi Tahoori
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

PDF.png
Paper

PDF.png
Slides

Logic Synthesis

title: Synthesis and Optimization of Switching Nanoarrays
authors: Ceylan Morgul and Mustafa Altun
presented at: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
(DDECS)
, Belgrade, Serbia, 2015.

PDF.png
Paper

PPT.jpg
Slides

Performance Modeling and Optimization

title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
accepted in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016.

PDF.png
Paper

title: Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
authors: Ceylan Morgul, Furkan Peker, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

PDF.png
Paper

PPT.jpg
Poster

Personal tools
Namespaces

Variants
Actions
NANOxCOMP
Toolbox