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| | <br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]] | | <br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]] |
| − | |}
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| − |
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| − | {| style="border:2px solid #abd5f5; background:#f1f5fc;"
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| − | |
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| − | {|
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| − | |- valign=top
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| − | | width="100" |'''title''':
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| − | | width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
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| − | |- valign="top"
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| − | | '''authors''':
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| − | | Ceylan Morgul, Furkan Peker, and [[Mustafa Altun]]
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| − | |- valign=top
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| − | | '''presented at''':
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| − | | [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
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| − | |}
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| − |
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| − | | align=center width="70" |
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| − | <span class="plainlinks">
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| − | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]</span>
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| − | <br>
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| − | [[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
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| − | | align="center" width="70" |
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| − | <span class="plainlinks">
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| − |
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| − | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]
| |
| − | </span>
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| − | <br> [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
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| − | |}
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| − |
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| − | {| style="border:2px solid #abd5f5; background:#f1f5fc;"
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| − | |
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| − | {|
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| − | |- valign=top
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| − | | width="100" |'''title''':
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| − | | width="550"|[[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Defect Tolerance in Diode FET and Four-Terminal Switch Based Nano-Crossbar Arrays]]
| |
| − | |- valign="top"
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| − | | '''authors''':
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| − | | Onur Tunali and [[Mustafa Altun]]
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| − | |- valign="top"
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| − | | '''presented at''':
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| − | | [http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], <br> Boston, USA, 2015.
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| − | |}
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| − | | align=center width="70" |
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| − | <span class="plainlinks">
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| − | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/ee/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf]]</span>
| |
| − | <br>
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| − | [[Media:Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pdf | Paper]]
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| − | | align="center" width="70" |
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| − | <span class="plainlinks">
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| − |
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| − | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx]]
| |
| − | </span>
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| − | <br> [http://www.ecc.itu.edu.tr/images/f/f9/Tunali_Altun_Defect_Tolerance_in_Diode_FET_and_Four-Terminal_Switch_based_Nano-Crossbar_Arrays.pptx Slides]
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| − | |}
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| − |
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| − | {| style="border:2px solid #abd5f5; background:#f1f5fc;"
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| − |
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| − | |
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| − | {|
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| − | |- valign=top
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| − | | width="100" |'''title''':
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| − | | width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]]
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| − | |- valign="top"
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| − | | '''authors''':
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| − | | Ceylan Morgul and [[Mustafa Altun]]
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| − | |- valign=top
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| − | | '''presented at''':
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| − | | [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems <br> (DDECS)], Belgrade, Serbia, 2015.
| |
| − | |}
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| − |
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| − | | align=center width="70" |
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| − | <span class="plainlinks">
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| − | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]</span>
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| − | <br>
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| − | [[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]]
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| − | | align="center" width="70" |
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| − | <span class="plainlinks">
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| − |
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| − | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]]
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| − | </span>
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| − | <br> [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides]
| |
| − | |}
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| − |
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| − | {| style="border:2px solid #abd5f5; background:#f1f5fc;"
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| − | |
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| − | {|
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| − | |- valign=top
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| − | | width="100" |'''title''':
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| − | | width="624"|[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Logic Synthesis for Switching Lattices]]
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| − | |- valign="top"
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| − | | '''authors''':
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| − | | [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
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| − | |- valign="top"
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| − | | '''appeared in''':
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| − | | [http://www.computer.org/portal/web/tc IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588–1600, 2012.
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| − | <!-- |- valign="top"
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| − | | '''presented at''':
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| − | | [http://fias.uni-frankfurt.de International Conference on Computational Modelling of Nanostructured Materials <br> (ICCMNM)-FIAS], Frankfurt, Germany, 2013. -->
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| − | |}
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| − | | align=center width="70" |
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| − | <span class="plainlinks">
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| − | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span>
| |
| − | <br>
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| − | [[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]]
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| − | |}
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| − |
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| − | {| style="border:2px solid #abd5f5; background:#f1f5fc;"
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| − | |
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| − | {|
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| − | |- valign=top
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| − | | width="100" |'''title''':
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| − | | width="624"|[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Synthesizing Logic with Percolation in Nanoscale Lattices]]
| |
| − | |- valign="top"
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| − | | '''authors''':
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| − | | [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
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| − | |- valign="top"
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| − | | '''appeared in''':
| |
| − | | [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description/ International Journal of Nanotechnology and Molecular Computation], Vol. 3, Issue 2, pp. 12–30, 2011.
| |
| − | |}
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| − |
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| − | | align=center width="70" |
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| − | <span class="plainlinks">
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| − | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3b/Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf]]</span>
| |
| − | <br>
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| − | [[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Paper]]
| |
| − | |}
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| − |
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| − | {| style="border:2px solid #abd5f5; background:#f1f5fc;"
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| − | |
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| − | {|
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| − | |- valign=top
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| − | | width="100" |'''title''':
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| − | | width="550"|[[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Lattice Based Computation of Boolean Functions]]
| |
| − | |- valign="top"
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| − | | '''authors''':
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| − | | [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
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| − | |- valign="top"
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| − | | '''presented at''':
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| − | | [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], Anaheim, USA, 2010.
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| − | |}
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| − | | align=center width="70" |
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| − | <span class="plainlinks">
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| − | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7b/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf]]</span>
| |
| − | <br>
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| − | [[Media:Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.pdf | Paper]]
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| − | | align="center" width="70" |
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| − | <span class="plainlinks">
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| − |
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| − | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt]]
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| − | </span>
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| − | <br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides]
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| − | |}
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| − |
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| − | {| style="border:2px solid #abd5f5; background:#f1f5fc;"
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| − |
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| − | |
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| − | {|
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| − | |- valign=top
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| − | | width="100" |'''title''':
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| − | | width="550"|[[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Nanoscale Digital Computation Through Percolation]]
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| − | |- valign="top"
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| − | | '''authors''':
| |
| − | | [[Mustafa Altun]], [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel], and [http://www.cbs.umn.edu/eeb/contacts/claudia-neuhauser/ Claudia Neuhauser]
| |
| − | |- valign=top
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| − | | '''presented at''':
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| − | | [http://www.dac.com IEEE/ACM Design Automation Conference (DAC)], San Francisco, USA, 2009.
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| − | |}
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| − |
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| − | | align=center width="70" |
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| − | <span class="plainlinks">
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| − | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0c/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf]]</span>
| |
| − | <br>
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| − | [[Media:Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.pdf | Paper]]
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| − | | align="center" width="70" |
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| − | <span class="plainlinks">
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| − |
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| − | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt]]
| |
| − | </span>
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| − | <br> [http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt Slides]
| |
| − | |}
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| − |
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| − | ==== National Publications in Turkish ====
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| − |
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| − | {| style="border:2px solid #abd5f5; background:#f1f5fc;"
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| − | |
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| − | {|
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| − | |- valign=top
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| − | | width="100" |'''title''':
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| − | | width="550"|[[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf | Anahtarlamalı Nano Dizinler ile Lojik Devre Tasarımı ve Boyut Optimizasyonu]]
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| − | |- valign="top
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| − | | '''authors''':
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| − | | Ceylan Morgul and [[Mustafa Altun]]
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| − | |- valign="top"
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| − | | '''presented at''':
| |
| − | | [http://www.eleco.org.tr/ Elektrik, Elektronik, Bilgisayar ve Biyomedikal Mühendisliği Sempozyumu (ELECO)], <br> Bursa, Turkey, 2014.
| |
| − | |}
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| − |
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| − | | align=center width="70" |
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| − | <span class="plainlinks">
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| − |
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| − | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/9/99/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf]]</span>
| |
| − | <br>
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| − | [[Media:Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pdf | Paper]]
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| − |
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| − | | align="center" width="70" |
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| − | <span class="plainlinks">
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| − |
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| − | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx]]
| |
| − | </span>
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| − | <br> [http://www.ecc.itu.edu.tr/images/a/aa/Morgul_Altun_Anahtarlamali_Nano_Dizinler_ile_Lojik_Devre_Tasarimi_ve_Boyut_Optimizasyonu.pptx Slides]
| |
| | |} | | |} |
| | | | |
