Research

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Our research is multidisciplinary and spans areas such as circuit design, emerging computing models, and mathematics. Our main goal is developing novel ways of computing for nanoscale technologies.
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We aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Our objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.  
  
== Computing with Networks of Nanoswitches ==
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<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div>
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Logic Synthesis </h2>
  
As current CMOS-based technology is approaching its anticipated limits, research is shifting to novel forms of nanoscale technologies including molecular-scale self-assembled systems. Unlike conventional CMOS that can be patterned in complex ways with lithography, self-assembled nanoscale systems generally consist of regular structures. Logical functions are achieved with crossbar-type switches. Our model, a network of four- terminal switches, corresponds to this type of switch in a variety of emerging technologies, including nanowire crossbar arrays and magnetic switch-based structures.
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=== Synthesis Problem ===
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We study '''implementation of Boolean functions''' with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with '''optimal array sizes'''.
In his seminal Master's Thesis, [http://en.wikipedia.org/wiki/Claude_Shannon Claude Shannon] made the connection between Boolean algebra and switching circuits. He considered '''two-terminal''' switches corresponding to electromagnetic relays. A Boolean function can be implemented in terms of connectivity across a network of switches, often arranged in a series/parallel configuration.  We have developed a method for synthesizing Boolean functions with networks of '''four-terminal switches''', arranged in rectangular lattices.
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[[Image:nanoarray_logic_synthesis.png|center|none|800px|link=]]
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[[Image:2-switch.png|center|thumb|none|400px|Shannon's model: '''two-terminal switches'''.  Each switch is either ON (closed) or OFF (open). A Boolean function is implemented in terms of connectivity across a network of switches, arranged in a series/parallel configuration. This network implements the function f = x_1 x_2 x_3 + x_1 x _2 x_5 x_6 + x_4 x_5 x_2 x_3 + x_4
 
x_5 x_6.]]
 
|| &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 
|| [[Image:4-switch.png|center|thumb|none|375px|Our model: '''four-terminal switches'''. Each switch is either mutually connected to its neighbors (ON) or disconnected (OFF).  A Boolean function is implemented in terms of connectivity between the top and bottom plates. This network implements the same function, f = x_1 x_2 x_3 + x_1 x _2 x_5 x_6 + x_4 x_5 x_2 x_3 + x_4
 
x_5 x_6.]]
 
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{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
 
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|- valign=top
 
|- valign=top
| width="696" |'''Selected Publication'''
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| width="696" |'''Selected Publications'''
 
|}
 
|}
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|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="450"|[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Logic Synthesis for Switching Lattices]]
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| width="450"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
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| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
|- valign="top"
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|- valign=top
| '''appeared&nbsp;in''':
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| [http://www.computer.org/portal/web/tc IEEE Transactions on Computers], <br>Vol. 61, Issue 11, pp. 1588&ndash;1600, 2012.
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|- valign="top"
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| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://www.dac.com Design Automation Conference], Anaheim, CA, 2010.
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| width="450"| [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016
 
|}
 
|}
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| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span>
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[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]]
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[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]]
 
| align="center" width="70" |  
 
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt]]
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[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides]
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<br> [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]]
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|}
 
|}
  
=== Robust Computation ===
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{| style="border:1px solid #abd5f5; background:#f1f5fc;"
  
We have devised a novel framework for digital computation with lattices of nanoscale switches with high defect rates, based on the mathematical phenomenon of [http://en.wikipedia.org/wiki/Percolation_theory percolation]. With random connectivity, percolation gives rise to a sharp non-linearity in the probability of global connectivity as a function of the probability of local connectivity. This phenomenon is exploited to compute Boolean functions robustly, in the presence of defects.
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|
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{|
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|- valign=top
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| width="100" |'''title''':
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| width="450"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]]
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|- valign="top"
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| '''authors''':
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| width="450"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
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|- valign=top
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| '''presented&nbsp;at''':
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| width="450"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
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|}
  
[[Image:Lattice-defects-percolation.jpg|left|thumb|none|900px|In a switching network with defects, percolation can be exploited to produce robust Boolean functionality. Unless the defect rate exceeds an error margin, with high probability no connection forms between the top and bottom plates for logical zero ("OFF"); with high probability, a connection forms for logical one ("ON").]]
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<span class="plainlinks">
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]</span>
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<br>
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[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]]
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| align="center" width="70" |
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<span class="plainlinks">
  
<br style="clear: both" />
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]
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</span>
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<br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
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|- valign=top
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| width="696" |'''Developed Tools'''
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|}
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
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|- valign=top
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| width="100" |'''title''':
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| width="524"|[[Media:Morgul_Altun_Optimal_Synthesis_Tools.zip | Optimal Synthesis Tool]]
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|- valign="top"
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| '''authors''':
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| Ceylan Morgul and Mustafa Altun
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|- valign="top"
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| '''description''':
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| width="524"| Two optimal synthesis tools Tool-1 and Tool-2 are developed in Matlab  and Python, respectively. Both tools aim to synthesize a given target Boolean functions with an optimal size of four-terminal switch based arrays . 
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|}
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| align=center width="70" |
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<span class="plainlinks">
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[[File:ZIP.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b3/Morgul_Altun_Optimal_Synthesis_Tools.zip]]</span>
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<br>
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[[Media:Morgul_Altun_Optimal_Synthesis_Tools.zip | Tool]]
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|}
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|}
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|-
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Fault Tolerance </h2>
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|-
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| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
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We examine reconfigurable crossbar arrays by considering randomly occurred '''stuck-open and stuck-closed crosspoint faults'''. In the presence of '''permanent''' faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of '''transient''' faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions
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Since '''density''' feature of crossbar architectures is the main attracting point, we perform a detailed yield analysis by considering both uniform and non-uniform defect distributions.
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We formalize an approximate successful mapping probability metric for uniform distributions
 +
and determine '''area overheads'''.
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 +
[[Image:nanoarray_fault_tolerance.png|center|none|500px|link=]]
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{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
 
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
  
 
|- valign=top
 
|- valign=top
| width="696" |'''Selected Publication'''
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| width="696" |'''Selected Publications'''
 
|}
 
|}
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
 
|
 
|
 
{|  
 
{|  
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="450"|[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Synthesizing Logic with Percolation in Nanoscale Lattices]]
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| width="524"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
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| Onur Tunali and Mustafa Altun
 
|- valign="top"
 
|- valign="top"
 
| '''appeared&nbsp;in''':
 
| '''appeared&nbsp;in''':
| [http://www.igi-global.com/Bookstore/TitleDetails.aspx?TitleId=1117&DetailsType=Description/ International Journal of Nanotechnology and Molecular Computation], <br>Vol. 3, Issue 2, pp. 12&ndash;30, 2011.
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| width="524" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017.
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|}
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| align=center width="70" |
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<span class="plainlinks">
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]</span>
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<br>
 +
[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]]
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|}
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{| style="border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
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|- valign=top
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| width="100" |'''title''':
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| width="450"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]]
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|- valign="top"
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| '''authors''':
 +
| Onur Tunali and [[Mustafa Altun]]
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|- valign="top"
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| '''accepted&nbsp;at''':
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| width="450"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017.
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|}
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| align=center width="70" |
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<span class="plainlinks">
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]</span>
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<br>
 +
[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]]
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| align="center" width="70" |
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<span class="plainlinks">
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[[File:PPT.jpg|60px|link=]]
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</span>
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<br> Slides
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|}
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
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|- valign=top
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| width="696" |'''Developed Tools'''
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|}
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
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|- valign=top
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| width="100" |'''title''':
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| width="524"|[[Media:Tunali_Altun_Fault_Tolerant_Logic_Mapping_Tool.zip | Fault Tolerant Logic Mapping Tool]]
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|- valign="top"
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| '''authors''':
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| Onur Tunali and Mustafa Altun
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|- valign="top"
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| '''description''':
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| width="524"| The tool is developed in Matlab. It aims to map logic funtions into fault crossbars such that each crosspoint has an independent fault probability up to 20%.
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|}
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| align=center width="70" |
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<span class="plainlinks">
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[[File:ZIP.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/16/Tunali_Altun_Fault_Tolerant_Logic_Mapping_Tool.zip]]</span>
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<br>
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[[Media:Tunali_Altun_Fault_Tolerant_Logic_Mapping_Tool.zip | Tool]]
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|}
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{| style="margin-left: auto; margin-right: 0px; border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
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|- valign=top
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| width="100" |'''title''':
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| width="524"|[[Media:Tunali_Altun_Yield_Analysis_Tool.zip | Yield Analysis Tool]]
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|- valign="top"
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| '''authors''':
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| Onur Tunali and Mustafa Altun
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|- valign="top"
 +
| '''description''':
 +
| width="524"| The tool is developed in Matlab. This tool calculates the required crossbar size in advance according to a given logic function and a defect rate. Tool accepts two parameters, logic function file and defect rate as inputs and returns the size of crossbar.
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|}
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| align=center width="70" |
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<span class="plainlinks">
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[[File:ZIP.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/15/Tunali_Altun_Yield_Analysis_Tool.zip]]</span>
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<br>
 +
[[Media:Tunali_Altun_Yield_Analysis_Tool.zip | Tool]]
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|}
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|}
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|}
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|-
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| colspan="2" style="background:#8FBCAF; text-align:center; padding:1px; border-bottom:1px #8FBCAF solid;" |
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<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Performance Modeling and Analysis </h2>
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|-
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| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
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We introduce an '''accurate capacitor-resistor model''' for nano-crossbar arrays that is to be used for '''power/delay/area''' performance analysis and optimization. In order to find capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies.
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[[Image:nanoarray_RC_modeling.png|center|none|500px|link=]]
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| width="696" |'''Selected Publications'''
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{| style="border:1px solid #abd5f5; background:#f1f5fc;"
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|
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{|
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|- valign=top
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| width="100" |'''title''':
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| width="450"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]]
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|- valign="top"
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| '''authors''':
 +
| Ceylan Morgul, Furkan Peker, and Mustafa Altun
 
|- valign=top
 
|- valign=top
 
| '''presented&nbsp;at''':
 
| '''presented&nbsp;at''':
| [http://www.dac.com Design Automation Conference], San Francisco, CA, 2009.
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| width="450"| [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016.
 
|}
 
|}
  
 
| align=center width="70" |  
 
| align=center width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/3/3b/Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf]]</span>
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[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Riedel_Synthesizing_Logic_with_Percolation_in_Nanoscale_Lattices.pdf | Paper]]
+
[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]]
 
| align="center" width="70" |  
 
| align="center" width="70" |  
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt]]
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]]
 
</span>
 
</span>
<br> [http://www.ecc.itu.edu.tr/images/f/fe/Altun_Riedel_Neuhauser_Nanoscale_Digital_Computation_Through_Percolation.ppt Slides]
+
<br> [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster]
 +
|}
 
|}
 
|}
  
 +
| style="border:1px solid transparent;" |
 +
<!--        PROJE      -->
  
== Mathematics ==
+
|}
 +
|}
  
=== Self-Duality Problem ===
 
  
The problem of testing whether a monotone Boolean function in irredundant disjuntive normal form (IDNF) is self-dual is one of few problems in circuit complexity whose precise tractability status is '''unknown'''. We have focused on this '''famous problem'''. We have shown that monotone self-dual Boolean functions in IDNF do not have more variables than disjuncts. We have proposed an algorithm to test whether a monotone Boolean function in IDNF with ''n'' variables and ''n'' disjuncts is self-dual. The algorithm runs in O(n^4) time.
+
{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
 +
|-
 +
| colspan="2" style="background:#8FBC9F; text-align:center; padding:1px; border-bottom:1px #8FBCAF solid;" |
 +
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Technology Development and Performance Optimization </h2>
 +
 
 +
|-
 +
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
 +
 
 +
Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures. Computing with crossbar arrays is achieved by its crosspoints behaving as switches, either two-terminal or four-terminal. Depending on the technology used, a two-terminal switch behaves as a diode, a resistive/memristive switch, or a field effect transistor (FET). On the other hand, a four-terminal switch has a unique behavior. While there have been many different technologies proposed for two-terminal switch based arrays, technology development for four-terminal switch based arrays, called switching lattices, has recently started.
 +
 
 +
For both two-terminal and four-terminal switch based arrays, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. We also aim to develeop CMOS-compatible technologies for crossbar arrays, specifically for switching lattices.
 +
 
 +
[[Image:Research_nano-2019.png|center|none|800px|link=]]
 +
 
 +
<h3>
 +
Technology Development</h3>
 +
 
 +
Although a four-terminal switch based array offers a '''significant area advantage''', in terms of the number of switches, compared to the ones having two-terminal switches, its realization at the technology level needs
 +
further justifications and raises a number of questions about its
 +
feasibility. We answer these questions. First, by using
 +
three dimensional technology computer-aided design (TCAD)
 +
simulations, we show that '''four-terminal switches can be directly implemented with the CMOS technology'''. For this purpose, we
 +
try different semiconductor gate materials in different formations
 +
of geometric shapes. Then, by fitting the TCAD simulation data
 +
to the standard CMOS current-voltage equations, we develop a
 +
Spice model of a four-terminal switch. Finally, we successfully
 +
perform '''Spice circuit simulations on four-terminal switches''' with
 +
different sizes.
 +
[[Image:research_lattice_technology.png|center|none|800px|link=]]
 +
 
 +
<h3>
 +
Performance Optimization</h3>
 +
 
 +
We study crossbar arrays including the memristive ones. We
 +
propose a '''defect-tolerant logic synthesis algorithms by considering area, delay, and power costs''' of the arrays.
 +
<!-- [[Image:Research-2.png|center|none|800px|link=]] -->
 +
 
 +
 
 +
<!--        YAYIN      -->
 +
{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"
 +
| class="MainPageBG" style="width:50%; border:0px solid #D8BFD8; vertical-align:top; color:#000;" |
 +
{| id="mp-left" style="width:100%; vertical-align:top;"
 +
 
 +
|
  
 
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
 
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
  
 
|- valign=top
 
|- valign=top
| width="696" |'''Selected Publication'''
+
| width="696" |'''Selected Publications'''
 
|}
 
|}
 +
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
  
 
|
 
|
{|  
+
{|
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="524"|[[Media:Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf | A Study on Monotone Self-dual Boolean Functions]]
+
| width="450"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="450"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and [[Mustafa Altun]]
 
|- valign=top
 
|- valign=top
 +
| '''presented&nbsp;at''':
 +
| width="450"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019.
 +
|}
 +
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]</span>
 +
<br>
 +
[[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides]
 +
|}
 +
 +
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="450"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]]
 +
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]] and [http://cadbio.com/wiki/index.php/Marc_Riedel Marc Riedel]
+
| Onur Tunali and [[Mustafa Altun]]
 
|- valign="top"
 
|- valign="top"
| '''submitted &nbsp;to''':
+
| '''appeared&nbsp;in''':
| [http://www.siam.org/journals/sidma.php SIAM Journal on Discrete Mathematics], 2012.
+
| width="450" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22&ndash;31, 2018.
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="450"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018.
 
|}
 
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]</span>
 +
<br>
 +
[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
  
| align=center width="70" |  
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides]
 +
|}
 +
 
 +
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="450"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]]
 +
|- valign="top"
 +
| '''authors''':
 +
| width="450"| Dan Alexandrescu, [[Mustafa Altun]], Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
 +
|- valign=top
 +
| '''appeared&nbsp;in''':
 +
| width="450" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14&ndash;25, 2017.
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="450"| [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016.
 +
|}
 +
 
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]]
 +
| align="center" width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/53/Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf]]</span>
+
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]]
 +
</span>
 +
<br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]]
 +
|}
 +
 
 +
<!--
 +
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="450"|[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Logic Synthesis for Switching Lattices]]
 +
|- valign="top"
 +
| '''authors''':
 +
| [[Mustafa Altun]] and Marc Riedel
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="450"| [http://www.computer.org/portal/web/tc IEEE Transactions on Computers], Vol. 61, Issue 11, pp. 1588&ndash;1600, 2012.
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| [http://www.dac.com Design Automation Conference (DAC)], Anaheim, USA, 2010.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/ca/Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Riedel_A_Study_on_Monotone_Self_Dual_Boolean_Functions.pdf | Paper]]
+
[[Media:Altun_Riedel_Logic_Synthesis_for_Switching_Lattices.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Riedel_Lattice-Based_Computation_of_Boolean_Functions.ppt Slides]
 
|}
 
|}
 +
-->
 +
|}
 +
| style="border:1px solid transparent;" |
 +
<!--        PROJE      -->
  
== Analog Circuit Design ==
 
  
=== Positive Feedback ===
+
|}
The conventional wisdom is that analog circuits should not include positive feedback loops. As controversial as it seems, we have successfully used '''positive feedback''' for impedance improvement in a current amplifier. With adding few transistors we have achieved very low input resistance values. We have tested the proposed fully-differential current amplifier in a filter application.
+
|}
 +
 
 +
 
 +
{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
 +
|-
 +
| colspan="2" style="background:#8FBC8F; text-align:center; padding:1px; border-bottom:1px #8FBC9F solid;" |
 +
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Complete Synthesis Methodology </h2>
 +
|-
 +
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
 +
 
 +
Due to the stochastic nature
 +
of nano-fabrication, nano arrays show different properties both
 +
in structural and physical device levels compared to conventional
 +
technologies. Mentioned factors introduce random characteristics
 +
that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic
 +
technology preference for switching elements, defect or fault rates
 +
of the given nano switching array and the variation values as well
 +
as their effects on performance metrics including power, delay, and
 +
area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization
 +
algorithms for each step of the process.
 +
 
 +
 
 +
[[Image:Research-synthesis-methodology.png|center|none|800px|link=]]
 +
 
 +
 
 +
<!--        YAYIN      -->
 +
{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"
 +
| class="MainPageBG" style="width:50%; border:0px solid #D8BFD8; vertical-align:top; color:#000;" |
 +
{| id="mp-left" style="width:100%; vertical-align:top;"
 +
 
 +
|
  
 
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
 
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
  
 
|- valign=top
 
|- valign=top
| width="696" |'''Selected Publication'''
+
| width="696" |'''Selected Publications'''
 
|}
 
|}
 +
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
  
 
|
 
|
{|  
+
{|
 
|- valign=top
 
|- valign=top
 
| width="100" |'''title''':
 
| width="100" |'''title''':
| width="524"|[[Media:Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf | Design of a Fully Differential Current Mode Operational Amplifier with its Filter Applications]]
+
| width="450"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]]
 
|- valign="top"
 
|- valign="top"
 
| '''authors''':
 
| '''authors''':
| [[Mustafa Altun]] and [http://web.itu.edu.tr/~kuntman/ Hakan Kuntman]
+
| width="450"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
 
|- valign="top"
 
|- valign="top"
| '''appeared &nbsp;in''':
+
| '''presented&nbsp;at''':
| [http://www.sciencedirect.com/science/journal/14348411 AEU International Journal of Electronics and Communications], <br>Vol. 62, Issue 3, pp. 39&ndash;44, 2008.
+
| width="450"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018.
 
|}
 
|}
  
| align=center width="70" |  
+
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]</span>
 +
<br>
 +
[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf | Paper]]
 +
| align="center" width="70" |
 
<span class="plainlinks">
 
<span class="plainlinks">
  
[[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e5/Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf]]</span>
+
[[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]]
 +
</span>
 +
<br> [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides]
 +
|}
 +
 
 +
|}
 +
 
 +
 
 +
{| id=portal cellspacing="0" cellpadding="0" width=100% style="border:1px solid #B8C7D9; padding:0px;"
 +
|-
 +
| colspan="2" style="background:#8FBC7F; text-align:center; padding:1px; border-bottom:1px #8FBC8F solid;" |
 +
<h2 style="margin:.1em; border-bottom:1px; font-size:140%; font-weight:bold;"> Crossbar Memories </h2>
 +
|-
 +
| valign="top" style="padding:8px 8px 0px 8px; background:#f5fffa;" <!--H210 S4 V100--> |
 +
 
 +
In this work, we investigated the sensing challenges of spin-transfer torque MRAMs structured as nano-crossbar memories. To overcome
 +
the problems of reading this type of memory, we have proposed a voltage sensing amplifier topology and compared its
 +
performance to that of the current sensing amplifier in terms of power, speed, and bit error rate performance.
 +
 
 +
[[Image:Crossbar-memory.png|center|none|500px|link=]]
 +
 
 +
<!--        YAYIN      -->
 +
{| id="mp-upper" style="width: 100%; margin:4px 0 0 0; background:none; border-spacing: 0px;"
 +
| class="MainPageBG" style="width:50%; border:0px solid #D8BFD8; vertical-align:top; color:#000;" |
 +
{| id="mp-left" style="width:100%; vertical-align:top;"
 +
 
 +
|
 +
 
 +
{| style="border:1px solid #abd5f5; background:#d0e5f5; padding:0.2em 0.5em; font-weight:bold;"
 +
 
 +
|- valign=top
 +
| width="696" |'''Selected Publications'''
 +
|}
 +
{| style="border:1px solid #abd5f5; background:#f1f5fc;"
 +
 
 +
|
 +
{|
 +
|- valign=top
 +
| width="100" |'''title''':
 +
| width="450"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]]
 +
|- valign="top"
 +
| '''authors''':
 +
| Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
 +
|- valign="top"
 +
| '''appeared&nbsp;in''':
 +
| width="450"| [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], accepted for publication, 2019.
 +
|- valign="top"
 +
| '''presented&nbsp;at''':
 +
| width="450"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017.
 +
|}
 +
| align=center width="70" |
 +
<span class="plainlinks">
 +
[[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]</span>
 
<br>
 
<br>
[[Media:Altun_Kuntman_Design_of_a_Fully_Differential_Current_Mode_Operational_Amplifier_with_its_Filter_Applications.pdf | Paper]]
+
[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]]
 +
| align="center" width="70" |
 +
<span class="plainlinks">
 +
 
 +
[[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]]
 +
</span>
 +
<br> [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides]
 +
|}
 +
 
 +
|}
 +
| style="border:1px solid transparent;" |
 +
<!--        PROJE      -->
 +
 
 +
|}
 
|}
 
|}

Latest revision as of 18:00, 13 May 2019

We aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. Our objectives are 1) synthesizing Boolean functions with area optimization; 2) achieving fault tolerance; 3) performing performance optimization by considering area, delay, power, and accuracy; 4) implementing arithmetic and memory elements; and 5) realizing a synchronous state machine.

Contents

Logic Synthesis

We study implementation of Boolean functions with nano-crossbar arrays where each crosspoint behaves as a diode, a FET, and a four-terminal switch. For these three types, we give array size formulations for a given Boolean function. Additionally, we focus on four-terminal switch based implementations and propose an algorithm that implements Boolean functions with optimal array sizes.

Nanoarray logic synthesis.png


Selected Publications
title: Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions
authors: Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco
presented at: International Conference on Very Large Scale Integration (VLSI-SoC), Tallinn, Estonia, 2016

PDF.png
Paper

PDF.png
Slides

title: Synthesis and Performance Optimization of a Switching Nano-crossbar Computer
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

PDF.png
Paper

PDF.png
Slides

Developed Tools
title: Optimal Synthesis Tool
authors: Ceylan Morgul and Mustafa Altun
description: Two optimal synthesis tools Tool-1 and Tool-2 are developed in Matlab and Python, respectively. Both tools aim to synthesize a given target Boolean functions with an optimal size of four-terminal switch based arrays .

ZIP.png
Tool


Fault Tolerance

We examine reconfigurable crossbar arrays by considering randomly occurred stuck-open and stuck-closed crosspoint faults. In the presence of permanent faults, a fast and accurate heuristic algorithm is proposed that uses the techniques of index sorting, backtracking, and row matching. In the presence of transient faults, tolerance analysis is performed by formally and recursively determining tolerable fault positions

Since density feature of crossbar architectures is the main attracting point, we perform a detailed yield analysis by considering both uniform and non-uniform defect distributions. We formalize an approximate successful mapping probability metric for uniform distributions and determine area overheads.

Nanoarray fault tolerance.png


Selected Publications
title: Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, Issue 5, pp. 747–760, 2017.

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Paper

title: Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions
authors: Onur Tunali and Mustafa Altun
accepted at: IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, 2017.

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Developed Tools
title: Fault Tolerant Logic Mapping Tool
authors: Onur Tunali and Mustafa Altun
description: The tool is developed in Matlab. It aims to map logic funtions into fault crossbars such that each crosspoint has an independent fault probability up to 20%.

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Tool

title: Yield Analysis Tool
authors: Onur Tunali and Mustafa Altun
description: The tool is developed in Matlab. This tool calculates the required crossbar size in advance according to a given logic function and a defect rate. Tool accepts two parameters, logic function file and defect rate as inputs and returns the size of crossbar.

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Tool


Performance Modeling and Analysis

We introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. In order to find capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies.

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Selected Publications
title: Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays
authors: Ceylan Morgul, Furkan Peker, and Mustafa Altun
presented at: IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, USA, 2016.

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Poster


Technology Development and Performance Optimization

Nano-crossbar arrays have emerged as a strong candidate technology to replace CMOS in near future. They are regular and dense structures. Computing with crossbar arrays is achieved by its crosspoints behaving as switches, either two-terminal or four-terminal. Depending on the technology used, a two-terminal switch behaves as a diode, a resistive/memristive switch, or a field effect transistor (FET). On the other hand, a four-terminal switch has a unique behavior. While there have been many different technologies proposed for two-terminal switch based arrays, technology development for four-terminal switch based arrays, called switching lattices, has recently started.

For both two-terminal and four-terminal switch based arrays, we aim to develop a complete synthesis and performance optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. We also aim to develeop CMOS-compatible technologies for crossbar arrays, specifically for switching lattices.

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Technology Development

Although a four-terminal switch based array offers a significant area advantage, in terms of the number of switches, compared to the ones having two-terminal switches, its realization at the technology level needs further justifications and raises a number of questions about its feasibility. We answer these questions. First, by using three dimensional technology computer-aided design (TCAD) simulations, we show that four-terminal switches can be directly implemented with the CMOS technology. For this purpose, we try different semiconductor gate materials in different formations of geometric shapes. Then, by fitting the TCAD simulation data to the standard CMOS current-voltage equations, we develop a Spice model of a four-terminal switch. Finally, we successfully perform Spice circuit simulations on four-terminal switches with different sizes.

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Performance Optimization

We study crossbar arrays including the memristive ones. We propose a defect-tolerant logic synthesis algorithms by considering area, delay, and power costs of the arrays.


Selected Publications
title: Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling
authors: Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun
presented at: Design, Automation and Test in Europe (DATE), Florence, Italy, 2019.

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title: Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
authors: Onur Tunali and Mustafa Altun
appeared in: IEEE Micro, Vol. 38, Issue 5, pp. 22–31, 2018.
presented at: Design, Automation and Test in Europe (DATE), Dresden, Germany, 2018.

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title: Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays
authors: Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori
appeared in: Microprocessors and Microsystems, Vol. 54, pp. 14–25, 2017.
presented at: Euromicro Conference on Digital System Design (DSD), Limassol, Cyprus, 2016.

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Complete Synthesis Methodology

Due to the stochastic nature of nano-fabrication, nano arrays show different properties both in structural and physical device levels compared to conventional technologies. Mentioned factors introduce random characteristics that need to be carefully considered by synthesis process. For instance, a competent synthesis methodology must consider basic technology preference for switching elements, defect or fault rates of the given nano switching array and the variation values as well as their effects on performance metrics including power, delay, and area. Presented synthesis methodology in this study comprehensively covers the all specified factors and provides optimization algorithms for each step of the process.


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Selected Publications
title: Integrated Synthesis Methodology for Crossbar Arrays
authors: Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun
presented at: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Athens, Greece, 2018.

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Crossbar Memories

In this work, we investigated the sensing challenges of spin-transfer torque MRAMs structured as nano-crossbar memories. To overcome the problems of reading this type of memory, we have proposed a voltage sensing amplifier topology and compared its performance to that of the current sensing amplifier in terms of power, speed, and bit error rate performance.

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Selected Publications
title: Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs
authors: Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy
appeared in: Microelectronics Journal, accepted for publication, 2019.
presented at: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Taormina, Italy, 2017.

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