Publications and Presentations
From NANOxCOMP H2020 Project
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− | == | + | All materials are subject to copyrights. |
+ | <div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div> | ||
+ | == Comprehensive Project Papers== | ||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
− | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx]] | |
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx Slides] | ||
+ | |} | ||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
|- valign=top | |- valign=top | ||
− | | width=" | + | | width="100" |'''title''': |
+ | | width="550"|[[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Logic Synthesis and Testing Techniques for Switching Nano-Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Mehdi Tahoori | ||
+ | |- valign=top | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 54, pp. 14–25, 2017. | ||
|} | |} | ||
− | + | | align=center width="70" | | |
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/0a/Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_EtAl_Synthesis_and_Testing_for_Switching_Nano_Crossbar_Arrays.pdf | Paper]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Computing with Nano-Crossbar Arrays: Logic Synthesis and Fault Tolerance]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Mustafa Altun, Valentina Ciriani, and Mehdi Tahoori |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
− | | [http://www. | + | | [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Lausanne, Switzerland, 2017. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/0/09/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/2/28/Altun_Ciriani_Tahoori_Computing_with_Nano-Crossbar_Arrays.pptx Slides] | ||
|} | |} | ||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | {| | + | | |
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Synthesis and Performance Optimization of a Switching Nano-crossbar Computer]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, and Mehdi Tahoori | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/a/ab/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/7f/Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Altun_EtAl_Synthesis_and_Performance_Optimization_of_a_Switching_Nano-crossbar_Computer_SLIDES.pdf | Slides]] | ||
+ | |} | ||
+ | |||
+ | == Papers on Logic Synthesis == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
|- valign=top | |- valign=top | ||
− | | width=" | + | | width="100" |'''title''': |
+ | | width="624"|[[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Levent Aksoy and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''accepted in''': | ||
+ | | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=12 IEEE Transactions on Computers], 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/e/e0/Aksoy_Altun_Realizations_with_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Aksoy_Altun_Realizations_with_Switching_Lattices.pdf | Paper]] | ||
|} | |} | ||
− | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media: Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf| A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Levent Aksoy and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/f/fe/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/5/54/Aksoy_Altun_SAT_based_Synthesis_of_Switching_Lattices.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Optimal and Heuristic Algorithms to Synthesize Lattices of Four-Terminal Switches]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Ceylan Morgul and Mustafa Altun |
|- valign="top" | |- valign="top" | ||
| '''appeared in''': | | '''appeared in''': | ||
− | | [http://www. | + | | width="624" | [http://www.journals.elsevier.com/integration Integration, the VLSI Journal], Vol. 64, pp. 60–70, 2019. |
|} | |} | ||
− | |||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/58/Morgul_Altun_Algorithms_for_Switching_Lattices.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_Altun_Algorithms_for_Switching_Lattices.pdf | Paper]] |
|} | |} | ||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | + | | | |
− | + | {| | |
|- valign=top | |- valign=top | ||
− | | width=" | + | | width="100" |'''title''': |
+ | | width="550"|[[Media:MICPRO2.pdf | Composition of Switching Lattices for Regular and for Decomposed Functions]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco | ||
+ | |- valign=top | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 60, pp. 207–218, 2018. | ||
+ | |||
|} | |} | ||
− | {| style="border: | + | | align=center width="70" | |
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/1a/MICPRO2.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:MICPRO2.pdf | Paper]] | ||
+ | |||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
| | | | ||
Line 67: | Line 202: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:MICPRO1.pdf | Enhancing Logic Synthesis of Switching Lattices by Generalized Shannon Decomposition Methods]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa |
+ | |- valign=top | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://www.journals.elsevier.com/microprocessors-and-microsystems/ Microprocessors and Microsystems], Vol. 56, pp. 193–202, 2018. | ||
+ | |||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/08/MICPRO1.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:MICPRO1.pdf | Paper]] | ||
+ | |||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis]] | ||
|- valign="top" | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco | ||
+ | |- valign=top | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http:// | + | | [http://dsd-seaa2017.ocg.at/dsd2017 Euromicro Conference on Digital System Design (DSD)], Vienna, Austria 2017. |
|} | |} | ||
+ | |||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www. | + | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/5c/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File: | + | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/1/19/Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf]] |
</span> | </span> | ||
− | <br> [ | + | <br> [[Media:Bernasconi_EtAl_Composition_of_Switching_Lattices_Autosymmetric_Functions_SLIDES.pdf | Slides]] |
|} | |} | ||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | {| | + | | |
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Synthesis on Switching Lattices of Dimension-Reducible Boolean Functions]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Anna Bernasconi, Valentina Ciriani, Luca Frontini, and Gabriella Trucco | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://ati.ttu.ee/vlsi-soc2016/ International Conference on Very Large Scale Integration (VLSI-SoC)], Tallinn, Estonia, 2016 | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d5/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/a2/Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Bernasconi_EtAl_Synthesis_on_Switching_Lattices_D_Reducible_SLIDES.pdf | Slides]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
|- valign=top | |- valign=top | ||
− | | width=" | + | | width="100" |'''title''': |
+ | | width="550"|[[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Logic Synthesis for Switching Lattices by Decomposition with P-Circuits]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, and Tiziano Villa | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://dsd-seaa2016.cs.ucy.ac.cy/index.php Euromicro Conference on Digital System Design (DSD)], Limassol, Cyprus, 2016. | ||
|} | |} | ||
− | {| style="border: | + | |
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/c9/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Bernasconi_EtAl_Logic_Synthesis_for_Switching_Lattices_P_Circuits_SLIDES.pdf | Slides]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
| | | | ||
Line 100: | Line 309: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Synthesis and Optimization of Switching Nanoarrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Ceylan Morgul and Mustafa Altun |
|- valign=top | |- valign=top | ||
+ | | '''appeared in''': | ||
+ | | width="550"| [http://www.springer.com/us/book/9783319253381 Low-Dimensional and Nanostructured Materials and Devices], Springer International Publishing, pp. 635–660, 2016. | ||
+ | |- valign="top" | ||
| '''presented at''': | | '''presented at''': | ||
− | | [http://www. | + | | width="550"| [http://www.ddecs2015.org/ IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)], Belgrade, Serbia, 2015. |
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/59/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf]]</span> |
<br> | <br> | ||
− | [[Media: | + | [[Media:Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pdf | Paper]] |
| align="center" width="70" | | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/ | + | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx]] |
</span> | </span> | ||
− | <br> [http://www.ecc.itu.edu.tr/images/ | + | <br> [http://www.ecc.itu.edu.tr/images/1/1a/Morgul_Altun_Synthesis_and_Optimization_of_Switching_Nanoarrays.pptx Slides] |
|} | |} | ||
− | == | + | == Papers on Fault Tolerance, Performance Modeling and Optimization == |
− | {| style="border: | + | {| style="border:2px solid #abd5f5; background:#f1f5fc;" |
+ | | | ||
+ | {| | ||
|- valign=top | |- valign=top | ||
− | | width=" | + | | width="100" |'''title''': |
+ | | width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019. | ||
|} | |} | ||
− | {| style="border: | + | | align=center width="70" | |
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
| | | | ||
Line 135: | Line 369: | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]] |
+ | |- valign="top | ||
+ | | '''authors''': | ||
+ | | Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
|- valign=top | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Testability of Switching Lattices in the Cellular Fault Model]] | ||
+ | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | [[ | + | | width="550"| Anna Bernasconi, Valentina Ciriani, and Luca Frontini |
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://dsd-seaa2019.csd.auth.gr/ Euromicro Conference on Digital System Design (DSD)], Chalkidiki, Greece, 2019. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/3/36/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for _Switching _Lattices.pdf | Paper]] | ||
+ | |||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/db/Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching_Lattices_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Bernasconi_Ciriani_Frontini_Cellular_Fault_Model_for_Switching _Lattices_SLIDES.pdf | Slides]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model]] | ||
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''authors''': |
− | | [http://www. | + | | width="550"| Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, and Elena Ioana Vatajelu |
+ | |||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | [http://tima.univ-grenoble-alpes.fr/conferences/lats/2019/ IEEE Latin American Test Symposium (LATS)], Santiago, Chile, 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/f/fd/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.nanoxcomp.itu.edu.tr/images/8/80/Anghel_EtAl_Fault_Mitigation_of_Switching_Lattices.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Testability of Switching Lattices.pdf |Testability of Switching Lattices in the Stuck at Fault Model]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Anna Bernasconi, Valentina Ciriani, and Luca Frontini | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://vlsi-soc.di.univr.it/ International Conference on Very Large Scale Integration (VLSI-SoC)], Verona, Italy 2018. | ||
|} | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/2/29/Testability_of_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Testability of Switching Lattices.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
− | [[File:PDF.png|65px|link=http://www. | + | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/9/9c/Testability_of_Switching_Lattices_Poster.pdf]] |
+ | </span> | ||
+ | <br> [[Media:Testability_of_Switching_Lattices_Poster.pdf | Poster]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Defect Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Onur Tunali, Ceylan Morgul, and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=40 IEEE Micro], Vol. 38, Issue 5, pp. 22–31, 2018. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf]]</span> | ||
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Morgul_Altun_Defect_Tolerant_Memristor_Crossbars.pdf | Paper]] |
|} | |} | ||
− | == | + | {| style="border:2px solid #abd5f5; background:#f1f5fc;" |
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Furkan Peker and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6687315 IEEE Transactions on Multi-Scale Computing Systems], Vol. 4, No. 4, pp. 522–532, 2018. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/7/71/Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Peker_Altun_Variation_Tolerant_Logic_Mapping_of_Nano_Crossbars.pdf | Paper]] | ||
+ | |} | ||
− | {| style="border: | + | {| style="border:2px solid #abd5f5; background:#f1f5fc;" |
+ | | | ||
+ | {| | ||
|- valign=top | |- valign=top | ||
− | | width=" | + | | width="100" |'''title''': |
+ | | width="550"|[[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf| Logic Synthesis and Defect Tolerance for Memristive Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Onur Tunali and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Dresden, Germany, 2018. | ||
|} | |} | ||
− | {| style="border: | + | | align=center width="70" | |
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/5/57/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/b/b8/Tunali_Altun_Logic_Synthesis_and_Defect_Tolerance_for_Memristive_Crossbars.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf| Yield Analysis of Nano-Crossbar Arrays for Uniform and Clustered Defect Distributions]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Onur Tunali and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://icecs2017.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Batumi, Georgia, 2017. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/6/6b/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Tunali_Altun_Nano_Crossbar_Yield_Analysis.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/6/62/Tunali_Altun_Nano_Crossbar_Yield_Analysis.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="624"|[[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | A Fast Logic Mapping Algorithm for Multiple-type-Defect Tolerance in Reconfigurable Nano-Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | Onur Tunali and Mustafa Altun |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''accepted in''': |
− | | [http:// | + | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245516 IEEE Transactions on Emerging Topics in Computing], DOI: 10.1109/TETC.2017.2755458, 2017. |
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/c9/Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Tunali_Altun_Multiple_type_Defect_Tolerance_in_Nano_Crossbar_Arrays.pdf | Paper]] | ||
|} | |} | ||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | A Survey of Fault Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Onur Tunali and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://csur.acm.org/ ACM Computing Surveys], Vol. 50, No. 6, Article 79, 2017. | ||
+ | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/bc/Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Tunali_Altun_A_Survey_of_Nano-crossbar_Fault_Tolerance.pdf | Paper]] | ||
+ | |} | ||
− | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/ | + | {| style="border:2px solid #abd5f5; background:#f1f5fc;" |
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="624"|[[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Onur Tunali and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems], Vol. 36, Issue 5, pp. 747–760, 2017. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/c/cc/Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf]]</span> | ||
<br> | <br> | ||
− | [[Media: | + | [[Media:Tunali_Altun_Permanent_and_Transient_Fault_Tolerance_for_Reconfigurable_Nano-Crossbar_Arrays.pdf | Paper]] |
|} | |} | ||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
− | {| | + | | |
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Ceylan Morgul, Furkan Peker, and Mustafa Altun | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | [http://www.isvlsi.org/ IEEE Computer Society Annual Symposium on VLSI (ISVLSI)], Pittsburgh, USA, 2016. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/8/8f/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/5/5a/Morgul_Peker_Altun_Power-Delay-Area_Performance_Modeling_and_Analysis_for_Nano-Crossbar_Arrays.pptx Poster] | ||
+ | |} | ||
+ | |||
+ | == Papers on Synthesis Methodology == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
|- valign=top | |- valign=top | ||
− | | width=" | + | | width="100" |'''title''': |
+ | | width="550"|[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun | ||
+ | |- valign=top | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7729 IEEE Transactions on Nanotechnology], early access, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Paper]] | ||
+ | |||
|} | |} | ||
− | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
| | | | ||
{| | {| | ||
|- valign=top | |- valign=top | ||
| width="100" |'''title''': | | width="100" |'''title''': | ||
− | | width=" | + | | width="550"|[[Media: Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Integrated Synthesis Methodology for Crossbar Arrays]] |
|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | | + | | width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Ioana Vatajelu, Valentina Ciriani, Lorena Anghel, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun |
|- valign="top" | |- valign="top" | ||
− | | ''' | + | | '''presented at''': |
− | | [http://www. | + | | width="550"|[http://www.nanoarch.org/ IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)], Athens, Greece, 2018. |
|} | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/b/b1/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Morgul_EtAl_Integrated_Synthesis_Methodology for_Crossbar_Arrays.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/b/bd/Morgul_EtAl_Integrated_Synthesis_Methodology_for_Crossbar_Arrays.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | == Papers on Emerging Crossbar Memories == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Sensing Schemes for STT-MRAMs structured with high TMR in low RA MTJs]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Mesut Atasoyu, Mustafa Altun, and Serdar Ozoguz | ||
+ | |- valign=top | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://www.journals.elsevier.com/microelectronics-journal Microelectronics Journal], Vol. 89, pp. 30-36, 2019. | ||
+ | |} | ||
| align=center width="70" | | | align=center width="70" | | ||
<span class="plainlinks"> | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/a/af/Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Atasoyu_Altun_Ozoguz_Sensing_Schemes_for_STT-MRAMs.pdf | Paper]] | ||
− | [[File:PDF.png|65px|link=http://www. | + | |} |
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Spin-Torque Memristor based Offset Cancellation Technique for Sense Amplifiers ]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Mesut Atasoyu, Mustafa Altun, Serdar Ozoguz, and Kaushik Roy | ||
+ | |- valign=top | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://smacd2017.unisa.it/ International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)], Taormina, Italy, 2017. | ||
+ | |} | ||
+ | |||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/d/d3/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf]]</span> | ||
<br> | <br> | ||
− | [[Media: | + | [[Media:Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pdf | Paper]] |
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.nanoxcomp.itu.edu.tr/images/7/7a/Atasoyu_EtAl_Spin-Torque_Memristor_based_Offset_Cancellation.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | == Papers on Technology Development == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Ismail Cevik, Levent Aksoy, and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx Slides] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media: Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf| Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Serzat Safaltin, Oguz Gencer, Ceylan Morgul, Levent Aksoy, Sebahattin Gurmen, Csaba Andras Moritz, and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.date-conference.com/ Design, Automation and Test in Europe (DATE)], Florence, Italy, 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/2/2c/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/7/71/Safaltin_EtAl_Technology_Development_for_Switching_Lattices.pptx Slides] | ||
|} | |} |
Latest revision as of 11:15, 3 December 2020
All materials are subject to copyrights.
Contents |
[edit] Comprehensive Project Papers
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[edit] Papers on Logic Synthesis
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[edit] Papers on Fault Tolerance, Performance Modeling and Optimization
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[edit] Papers on Synthesis Methodology
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[edit] Papers on Emerging Crossbar Memories
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[edit] Papers on Technology Development
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