Publications and Presentations
From NANOxCOMP H2020 Project
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<div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div> | <div style="float:center; font-size:110%; font-weight:bold; clear:both; padding:0; margin:0.0em;">__TOC__</div> | ||
== Comprehensive Project Papers== | == Comprehensive Project Papers== | ||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Nano-Crossbar based Computing: Lessons Learned and Future Directions]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Mustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, and Csaba Andras Moritz | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/0/04/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/9/9f/Altun_EtAl_NANOxCOMP_Lessons_Learned_Future_Directions.pptx Slides] | ||
+ | |} | ||
+ | |||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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|- valign="top" | |- valign="top" | ||
| '''authors''': | | '''authors''': | ||
− | | Levent Aksoy and | + | | Levent Aksoy and Mustafa Altun |
|- valign="top" | |- valign="top" | ||
| '''accepted in''': | | '''accepted in''': | ||
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== Papers on Fault Tolerance, Performance Modeling and Optimization == | == Papers on Fault Tolerance, Performance Modeling and Optimization == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Sirakoulis_ICECS_Memristor_Networks.pdf| Noise-induced Performance Enhancement of Variability-aware Memristor Networks]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Vasileios Ntinas, Iosif-Angelos Fyrigos, Georigos Sirakoulis, Antonio Rubio, Javier Martín-Martinez, Rosana Rodriguez, and Montserrat Nafria | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.ieee-icecs2019.org/ IEEE International Conference on Electronics Circuits and Systems (ICECS)], Genova, Italy, 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/4/41/Sirakoulis_ICECS_Memristor_Networks.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Sirakoulis_ICECS_Memristor_Networks.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/c/cf/Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf]] | ||
+ | </span> | ||
+ | <br> [[Media:Sirakoulis_ICECS_Memristor_Networks_SLIDES.pdf | Slides]] | ||
+ | |} | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Analog Neural Network based on Memristor Crossbar Arrays]] | ||
+ | |- valign="top | ||
+ | | '''authors''': | ||
+ | | Hacer Yildiz, Mustafa Altun, Dogus Gungordu, and Mircea Stan | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | width="550"| [http://www.eleco.org.tr/ International Conference on Electrical and Electronics Engineering (ELECO)], Bursa, Turkey, 2019. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/8/84/Yildiz_Crossbar_Analog_Neural_Network.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Yildiz_Crossbar_Analog_Neural_Network.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.nanoxcomp.itu.edu.tr/images/b/b5/Yildiz_Crossbar_Analog_Neural_Network.pptx Slides] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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== Papers on Synthesis Methodology == | == Papers on Synthesis Methodology == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | |||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization with Fault Tolerance]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | width="550"| Ceylan Morgul, Luca Frontini, Onur Tunali, Lorena Anghel, Valentina Ciriani, Ioana Vatajelu, Csaba Moritz, Mircea Stan, Dan Alexandrescu, and Mustafa Altun | ||
+ | |- valign=top | ||
+ | | '''appeared in''': | ||
+ | | width="624" | [http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=7729 IEEE Transactions on Nanotechnology], early access, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.ecc.itu.edu.tr/images/d/db/Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Morgul_EtAl_Circuit_Design_Steps_for_Nano_Crossbar_Arrays.pdf | Paper]] | ||
+ | |||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
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== Papers on Technology Development == | == Papers on Technology Development == | ||
+ | |||
+ | {| style="border:2px solid #abd5f5; background:#f1f5fc;" | ||
+ | | | ||
+ | {| | ||
+ | |- valign=top | ||
+ | | width="100" |'''title''': | ||
+ | | width="550"|[[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | CMOS Implementation of Switching Lattices]] | ||
+ | |- valign="top" | ||
+ | | '''authors''': | ||
+ | | Ismail Cevik, Levent Aksoy, and Mustafa Altun | ||
+ | |- valign="top" | ||
+ | | '''presented at''': | ||
+ | | [http://www.date-conference.com/ Design, Automation, and Test in Europe (DATE)], Grenoble, France, 2020. | ||
+ | |} | ||
+ | | align=center width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | [[File:PDF.png|65px|link=http://www.nanoxcomp.itu.edu.tr/images/5/50/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf]]</span> | ||
+ | <br> | ||
+ | [[Media:Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pdf | Paper]] | ||
+ | | align="center" width="70" | | ||
+ | <span class="plainlinks"> | ||
+ | |||
+ | [[File:PPT.jpg|60px|link=http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx]] | ||
+ | </span> | ||
+ | <br> [http://www.ecc.itu.edu.tr/images/1/1c/Cevik_Aksoy_Altun_CMOS_Implementation_of_Switching_Lattices.pptx Slides] | ||
+ | |} | ||
{| style="border:2px solid #abd5f5; background:#f1f5fc;" | {| style="border:2px solid #abd5f5; background:#f1f5fc;" |
Latest revision as of 11:15, 3 December 2020
All materials are subject to copyrights.
Contents |
[edit] Comprehensive Project Papers
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[edit] Papers on Logic Synthesis
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[edit] Papers on Fault Tolerance, Performance Modeling and Optimization
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[edit] Papers on Synthesis Methodology
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[edit] Papers on Emerging Crossbar Memories
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[edit] Papers on Technology Development
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